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dac3154 dac3164 www.ti.com slas960 ? may 2013 dual 12-/10-bit 500 msps digital-to-analog converters check for samples: dac3154 , dac3164 1 features applications 2 ? dual channel ? multi-carrier, multi-mode cellular infrastructure base stations ? resolution ? radar ? dac3154: 10-bit ? signal intelligence ? dac3164: 12-bit ? software-defined radio ? maximum sample rate: 500 msps ? test and measurement instrumentation ? pin compatible family with dac3174 and dac3151/dac3161/dac3171 description ? input interface: the dac3154/dac3164 are dual channel 10-/12-bit, ? 12-/10-bit wide lvds inputs pin-compatible family of 500 msps digital-to-analog ? internal fifo converters (dac). the dac3154/dac3164 use a 10- /12-bit wide lvds digital bus with an input fifo. ? chip to chip synchronization fifo input and output pointers can be synchronized ? power dissipation: 460mw across multiple devices for precise signal ? spectral performance at 20 mhz if synchronization. the dac outputs are current sourcing and terminate to gnd with a compliance ? snr: 62 dbfs for dac3154, 72 dbfs for range of ? 0.5 to 1v. dac3154/ dac3164 are pin dac3164 compatible with the dual-channel, 14-bit, 500 msps ? sfdr: 76 dbc for dac3154, 77 dbc for digital-to-analog converters dac3174, and the single- dac3164 channel, 14-/12-10-bit, digital-to-analog converters ? current sourcing dacs dac3171/dac3161/dac3151. ? compliance range: ? 0.5v to 1v the devices are available in a qfn-64 powerpad ? ? package: 64 pin qfn (9x9mm) package is specified over the full industrial temperature range ( ? 40 c to 85 c). 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powerpad is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
dac3154 dac3164 slas960 ? may 2013 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. block diagrams figure 1. dac3154 2 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 100 de-interleave 10 100 10-b daca 10-b dacb control interface clock distribution extio biasj ioutap ioutan ioutbp ioutbn dacclkp dacclkn dataclkp dataclkn data9p data9n syncp syncn alignp alignn qmc a-offset qmc b-offset sdo sdio sdenb sclk txenable resetb vdda33 clkvdd18 digvdd18 vfuse vdda18 gnd lvpecl lvds lvpecl lvds 100 lvds 8 sample fifo 10 dacb gain programmable delay alarm sleep testmode iovdd 1.2 v reference 100 pattern test data0p data0n lvds daca gain optional input used for multi-dac sync
dac3154 dac3164 www.ti.com slas960 ? may 2013 figure 2. dac3164 copyright ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: dac3154 dac3164 100 de-interleave 12 100 12-b daca 12-b dacb control interface clock distribution extio biasj ioutap ioutan ioutbp ioutbn dacclkp dacclkn dataclkp dataclkn data11p data11n syncp syncn alignp alignn qmc a-offset qmc b-offset sdo sdio sdenb sclk txenable resetb vdda33 clkvdd18 digvdd18 vfuse vdda18 gnd lvpecl lvds lvpecl lvds 100 lvds 8 sample fifo 12 dacb gain programmable delay alarm sleep testmode iovdd 1.2 v reference 100 pattern test data0p data0n lvds daca gain optional input used for multi-dac sync
dac3154 dac3164 slas960 ? may 2013 www.ti.com pinout ? dac3154 pin assignment table ? dac3154 pin i/o description name no. control/serial sclk 43 i serial interface clock. internal pull-down. sdenb 42 i serial interface clock. internal pull-up. sdio 44 i/o bi-directional serial data in 3 pin mode (default). in 4-pin interface mode (register xyz), the sdio pin in an input only. internal pull-down. sdo 46 o uni-directional serial interface data in 4 pin mode (register xyz). the sdo pin is tri-stated in 3-pin interface mode (default). internal pulldown. resetb 41 i serial interface reset input. active low. initialized internal registers during high to low transition. assynchronous. internal pull-up. alarm 47 o cmos output for alarm condition. txenable 48 i transmit enable active high input. txenable must be high for the data to the dac to be enabled. when txenable is low, the digital logic section is forced to all 0, and any input data is ignored. internal pull-down. sleep 49 i puts device in sleep, active high. internal pull-down. 4 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dacclkp dacclkn alignp alignn syncp syncn vfuse (msb) d9p d9n d8p d8n d7p d7n d6p d6n nc txenable alarm sdo iovdd sdio sclk sdenb resetb nc nc nc nc nc nc nc d5p d5n d4p d4n d3p d3n dataclkp dataclkn d2p d2n digvdd18 d1p d1n (lsb) d0p d0n gnd pad (backside) dac3154 sleep ioutap ioutan vdda33 extio biasj ioutbn ioutbp clkvdd18 digvdd18 vdda18 nc nc vdda33 vdda33 nc nc vdda18
dac3154 dac3164 www.ti.com slas960 ? may 2013 pin assignment table ? dac3154 (continued) pin i/o description name no. data interface data[9:0]p/n 9/10- i lvds input data bits for both channels. each positive/negative lvds pair has an internal 100 19/20 termination resistor. data format relative to dataclkp/n clock is double data rate (ddr) with two data transfers per datackp/n clock cycle. 22/23 26/27- the data format is interleaved with channel a (rising edge) and channel b falling edge. 31/32 in the default mode (reverse bus not enabled): data9p/n is most significant data bit (msb) data0p/n is most significant data bit (lsb) dataclkp/n 24/25 i ddr differential input data clock. edge to center nominal timing. ch a rising edge, ch b falling edge in multiplexed output mode. syncp/n 6/7 i reset the fifo or to be used as a syncing source. these two functions are captured with the rising edge of dataclkp/n. the signal captured by the falling edge of dataclkp/n. alignp/n 4/5 i lvpecl fifo output syncrhonization. this positive/negative pair is captured with the rising edge of dacclkp/n. it is used to reset the clock dividers and for multiple dac synchronization. if unused it can be left unconnected. output/clock dacclkp/n 1/2 i lvpecl clock input for dac core with a self-bias of approximately clkvdd18/2. ioutap/n 61/60 o a-channel dac current output. an offset binary data pattern of 0x0000 at the dac input results in a full scale current source and the most positive voltage on the ioutap pin. similarly, a 0xffff data input results in a 0 ma current source and the least positive voltage on the ioutap pin. ioutbp/n 53/54 o b-channel dac current output. an offset binary data pattern of 0x0000 at the dac input results in a full scale current source and the most positive voltage on the ioutbp pin. similarly, a 0xffff data input results in a 0 ma current source and the least positive voltage on the ioutbp pin. reference extio 58 i/o used as external reference input when internal reference is disabled. requires a 0.1 f decoupling capacitor to gnd when used as reference output. biasj 57 o full-scale output current bias. for 20 ma full-scale output current, connect a 960 resistor to gnd. power supply iovdd 45 i supply voltage for cmos io ? s. 1.8v ? 3.3v. clkvdd18 3 i 1.8v clock supply digvdd18 21, 28 i 1.8v digital supply. also supplies lvds receivers. vdda18 50, 64 i analog 1.8v supply vdda33 55, 56, i analog 3.3v supply 59 vfuse 8 i digital supply voltage. (1.8v) this supply pin is also used for factory fuse programming. connect to dvdd pins for normal operation. nc 33-40, not used. these pins can be left open or tied to ground in actual application use. 51, 52, 62, 63 copyright ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com pinout ? dac3164 pin assignment table ? dac3164 pin i/o description name no. control/serial sclk 43 i serial interface clock. internal pull-down. sdenb 42 i serial interface clock. internal pull-up. sdio 44 i/o bi-directional serial data in 3 pin mode (default). in 4-pin interface mode (register xyz), the sdio pin in an input only. internal pull-down. sdo 46 o uni-directional serial interface data in 4 pin mode (register xyz). the sdo pin is tri-stated in 3-pin interface mode (default). internal pulldown. resetb 41 i serial interface reset input. active low. initialized internal registers during high to low transition. assynchronous. internal pull-up. alarm 47 o cmos output for alarm condition. txenable 48 i transmit enable active high input. txenable must be high for the data to the dac to be enabled. when txenable is low, the digital logic section is forced to all 0, and any input data is ignored. internal pull-down. sleep 49 i puts device in sleep, active high. internal pull-down. 6 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dacclkp dacclkn alignp alignn syncp syncn vfuse (msb) d11p d11n d10p d10n d9p d9n d8p d8n d1p txenable alarm sdo iovdd sdio sclk sdenb resetb nc nc nc nc d0n d0p (lsb) d1n d7p d7n d6p d6n d5p d5n dataclkp dataclkn d4p d4n digvdd18 d3p d3n d2p d2n gnd pad (backside) dac3164 sleep ioutap ioutan vdda33 extio biasj ioutbn ioutbp clkvdd18 digvdd18 vdda18 nc nc vdda33 vdda33 nc nc vdda18
dac3154 dac3164 www.ti.com slas960 ? may 2013 pin assignment table ? dac3164 (continued) pin i/o description name no. data interface data[11:0]p/n 9/10- i lvds input data bits for both channels. each positive/negative lvds pair has an internal 100 19/20 termination resistor. data format relative to dataclkp/n clock is double data rate (ddr) with two data transfers per datackp/n clock cycle. 22/23, 26-27- the data format is interleaved with channel a (rising edge) and channel b falling edge. 35/36 in the default mode (reverse bus not enabled): data11p/n is most significant data bit (msb) data0p/n is most significant data bit (lsb) dataclk[:0]p/n 24/25 i ddr differential input data clock. edge to center nominal timing. ch a rising edge, ch b falling edge in multiplexed output mode. syncp/n 6/7 i reset the fifo or to be used as a syncing source. these two functions are captured with the rising edge of dataclkp/n. the signal captured by the falling edge of dataclkp/n. alignp/n 24/25 i lvpecl fifo output syncrhonization. this positive/negative pair is captured with the rising edge of dacclkp/n. it is used to reset the clock dividers and for multiple dac synchronization. if unused it can be left unconnected. output/clock dacclkp/n 1/2 i lvpecl clock input for dac core with a self-bias of approximately clkvdd18/2. ioutap/n 61/60 o a-channel dac current output. an offset binary data pattern of 0x0000 at the dac input results in a full scale current source and the most positive voltage on the iouta1 pin. similarly, a 0xffff data input results in a 0 ma current source and the least positive voltage on the iouta1 pin. the iouta2 pin is the complement of iouta1. ioutbp/n 53/54 o b-channel dac current output. an offset binary data pattern of 0x0000 at the dac input results in a full scale current source and the most positive voltage on the ioutb1 pin. similarly, a 0xffff data input results in a 0 ma current source and the least positive voltage on the ioutb1 pin. the ioutb2 pin is the complement of ioutb1. reference extio 58 i/o used as external reference input when internal reference is disabled. requires a 0.1 f decoupling capacitor to gnd when used as reference output. biasj 57 o full-scale output current bias. for 20 ma full-scale output current, connect a 960 resistor to gnd. power supply iovdd 45 i supply voltage for cmos io ? s. 1.8v ? 3.3v. clkvdd18 3 i 1.8v clock supply digvdd18 21, 28 i 1.8v digital supply. also supplies lvds receivers. vdda18 50, 64 i analog 1.8v supply vdda33 55, 56, i analog 3.3v supply 59 vfuse 8 i digital supply voltage. (1.8v) this supply pin is also used for factory fuse programming. connect to dvdd pins for normal operation. nc 37, 38, not used. these pins can be left open or tied to ground in actual application use. 39, 40, 51, 52 62, 63 package/ordering information (1) specified package- package ordering transport product temperature eco plan quantity lead designator number media range dac3154irgct 250 dac3154 dac3154irgcr 2000 green (rohs qfn-64 rgc ? 40 c to 85 c dac3164irgc25 tape and reel 25 and no sb/br) dac3164 dac3164irgct 250 DAC3164IRGCR 2000 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com. copyright ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) value unit vdda33 to gnd ? 0.5 to 4 vdda18 to gnd ? 0.5 to 2.3 supply voltage clkvdd18 to gnd ? 0.5 to 2.3 v iovdd to gnd ? 0.5 to 4 digvdd18 to gnd ? 0.5 to 2.3 clkvdd18 to digvdd18 ? 0.5 to 0.5 vdda18 to digvdd18 ? 0.5 to 0.5 d[11..0]p, d[11..0]n, dataclkp, dataclkn, syncp, syncn to gnd ? 0.5 to digvdd18 + 0.5 terminal voltage dacclkp, dacclkn, alignp, alignn ? 0.5 to clkvdd18 + 0.5 v range txenable, alarm, sdo, sdio, sclk, sdenb, resetb to gnd ? 0.5 to iovdd + 0.5 ioutap, ioutan, ioutbp, ioutbn to gnd ? 0.7 to 1.4 extio, biasj to gnd ? 0.5 to vdda33 + 0.5 storage temperature range ? 65 to 150 c esd, human body model 2 kv (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. thermal information dac3174 thermal metric (1) units qfn (64 pin) ja junction-to-ambient thermal resistance 23.0 jctop junction-to-case (top) thermal resistance 7.6 jb junction-to-board thermal resistance 2.8 c/w jt junction-to-top characterization parameter 0.1 jb junction-to-board characterization parameter 2.8 jcbot junction-to-case (bottom) thermal resistance 0.2 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 8 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 electrical characteristics ? dc specifications typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, dac sample rate = 500msps, 50% clock duty cycle, vdda33/iovdd = 3.3v, vdda18/clkvdd18/digvdd18 = 1.8v, iout fs = 20ma (unless otherwise noted). dac3154 dac3164 parameter test conditions unit min typ max min typ max resolution 10 12 bits dc accuracy dnl differential nonlinearity 1 lsb = iout fs /2 10 for 0.04 0.2 dac3154; 1 lsb = iout fs /2 12 lsb inl integral nonlinearity 0.15 0.5 for dac3164 analog outputs coarse gain linearity 0.4 0.4 lsb offset error mid code offset 0.01 0.01 %fsr with external reference 2 2 gain error %fsr with internal reference 2 2 gain mismatch with internal reference -2 2 -2 2 %fsr minimum full scale output current 2 2 nominal full-scale current, ma iout fs = 16xibais current maximum full scale output current 20 20 output compliance range ioutfs = 20 ma -0.5 -0.5 1 v output resistance 300 300 k output capacitance 5 5 pf reference output v ref reference output voltage 1.14 1.2 1.26 1.14 1.2 1.26 v reference output current 100 100 na reference input vextio input voltage range external reference mode 0.1 1.2 1.25 0.1 1.2 1.25 v input resistance 1 1 m small signal bandwidth 500 500 khz input capacitance 100 100 pf temperature coefficients ppm of offset drift 1 1 fsr/ c with external reference 15 15 gain drift with internal reference 30 30 reference voltage drift 8 8 ppm / c power supply digvdd18, vfuse, vdda18, 1.71 1.8 1.71 1.8 1.89 v clkvdd18 vdda33 3.15 3.3 3.15 3.3 3.45 v sets cmos io voltage levels. iovdd 1.71 1.71 3.45 v nominal 1.8v, 2.5v or 3.3v copyright ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com electrical characteristics ? dc specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, dac sample rate = 500msps, 50% clock duty cycle, vdda33/iovdd = 3.3v, vdda18/clkvdd18/digvdd18 = 1.8v, iout fs = 20ma (unless otherwise noted). dac3154 dac3164 parameter test conditions unit min typ max min typ max power consumption i vdda33 3.3v analog supply current 52 59 52 59 ma i clkvdd18 1.8v clock supply current 49 67 49 57 ma mode 1 1.8v digital supply current f dac = 491.52 msps, i digvdd18 115 130 115 130 ma (digvdd18 and vfuse) qmc on, if = 20 mhz i iovdd 1.8v io supply current 0.002 0.015 0.002 0.015 ma p dis total power dissipation 464 530 464 530 mw i vdda33 3.3v analog supply current 51 51 ma i clkvdd18 1.8v clock supply current 38 38 ma mode 2 1.8v digital supply current f dac = 320 msps, i digvdd18 87 87 ma (digvdd18 and vfuse) qmc on, if = 20 mhz i iovdd 1.8v io supply current 0.002 0.002 ma p dis total power dissipation 396 396 mw i vdda33 3.3v analog supply current 2.6 2.6 ma i clkvdd18 1.8v clock supply current 43 43 ma mode 3 1.8v digital supply current sleep mode, i digvdd18 110 110 ma (digvdd18 and vfuse) f dac = 491.52 msps, dac in sleep mode i iovdd 1.8v io supply current 0.003 0.003 ma p dis total power dissipation 284 284 mw i vdda33 3.3v analog supply current 1.6 4 1.6 4 ma i clkvdd18 1.8v clock supply current 1.8 4 1.8 4 ma mode 4 1.8v digital supply current power-down mode, i digvdd18 1.7 3 ma (digvdd18 and vfuse) no clock, dac in sleep mode i iovdd 1.8v io supply current 0.003 0.015 0.003 0.015 ma p dis total power dissipation 10 26 10 26 mw psrr power supply rejection ratio dc tested ? 0.4 0.4 -0.4 0.4 %/fsr/v t operating temperature ? 40 85 -40 85 c 10 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 electrical characteristics ? ac specifications typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, dac sample rate = 500msps, 50% clock duty cycle, vdda33/iovdd = 3.3v, vdda18/clkvdd18/digvdd18 = 1.8v, iout fs = 20ma (unless otherwise noted). dac3154 dac3164 parameter test conditions unit min typ max min typ max analog output f dac maximum sample rate 500 500 msps output settling time to t s(dac) transition: code 0x0000 to 0x3fff 11 11 ns 0.1% t pd output propagation delay does not include digital latency 2 2 ns output rise time 10% to t r(iout) 200 200 ps 90% output fall time 90% to t f(iout) 200 200 ps 10% length of delay from dac input pins to data at digital latency output pins. in normal operation mode including the 26 26 s latency of fifo. ac performance f dac = 500 msps, f out = 10.1 mhz 81 82 spurious free dynamic sfdr f dac = 500 msps, f out = 20.1 mhz 76 77 dbc range f dac = 500 msps, f out = 70.1 mhz 69 70 f dac = 500 msps, f out = 10.1 0.5 mhz 82 83 f dac = 500 msps, f out = 20.1 0.5 mhz 81 82 imd3 intermodulation distortion dbc f dac = 500 msps, f out = 70.1 0.5 mhz 73.5 74 f dac = 500 msps, f out = 150.1 0.5 mhz 61 61 f dac = 500 msps, f out = 10.1 mhz 147 158 nsd noise spectral density f dac = 500 msps, f out = 20.1 mhz 146 156 dbc/hz f dac = 500 msps, f out = 70.1 mhz 146 153 f dac = 491.52 msps, f out = 30.72 mhz, 69 77 wcdma tm1 adjacent channel leakage aclr dbc ratio f ac = 491.52 msps, f out = 153.6 mhz, 68 73 wcdma tm1 f dac = 500 msps, channel isolation 90 90 dbc f out = 20 mhz copyright ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com electrical characteristics ? digital specifications typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, dac sample rate = 500msps, 50% clock duty cycle, vdda33/iovdd = 3.3v, vdda18/clkvdd18/digvdd18 = 1.8v, iout fs = 20ma (unless otherwise noted). dac3154 dac3164 parameters test conditions unit min typ max min typ max cmos digital inputs (resetb, sdenb, sclk, sdio, txenable) 0.6x 0.6x v ih high-level input voltage v iovdd iovdd 0.25 0.25 iovdd = 3.3 v, 2.5 v v il low-level input voltage v iovdd iovdd or 1.8 v i ih high-level input current ? 40 40 -40 40 a i il low-level input current ? 40 40 -40 40 a digital outputs ? cmos interface (sdout, sdio) iovdd = 3.3 v, 2.5 v, 0.85 0.85 v oh high-level output voltage v or 1.8 v iovdd iovdd 0.125 0.125 v ol low-level output voltage v iovdd iovdd serial port timing setup time, sdenb to rising edge of t s(sendb) 20 20 ns sclk t s(sdio) setup time, sdio to rising edge of sclk 10 10 ns t h(sdio) hold time, sdio from rising edge of sclk 5 5 ns t (sclk) period of sclk 100 100 ns t (sclkh) high time of sclk 40 40 ns t (sclkl) low time of sclk 40 40 ns data output delay after falling edge of t d(data) 10 10 ns sclk t reset minimum restb pulsewidth lvds interface (d[x..0]p/n, da[x..0]p/n , db[x..0]p/n , da_clkp/n, db_clkp/n, dataclkp/n, syncp/n, alignp/n) logic high differential input voltage v a,b+ 175 175 mv threshold logic low differential input voltage v a,b ? -175 ? 175 mv threshold v com input common mode range 1.0 1.2 2.0 1.0 1.2 2.0 v z t internal termination 85 110 135 85 110 135 c l lvds input capacitance 2 2 pf 12 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 electrical characteristics ? digital specifications (continued) typical values at t a = 25 c, full temperature range is t min = ? 40 c to t max = 85 c, dac sample rate = 500msps, 50% clock duty cycle, vdda33/iovdd = 3.3v, vdda18/clkvdd18/digvdd18 = 1.8v, iout fs = 20ma (unless otherwise noted). dac3154 dac3164 parameters test conditions unit min typ max min typ max lvds input timing: single bus single clock mode config3 setting datadly clkdly 0 0 -20 -20 0 1 -120 -120 0 2 -220 -220 0 3 -310 -310 0 4 -390 -390 0 5 -480 -480 setup d[x..0] valid to dataclk rising or t s(data) 0 6 -560 -560 ps time falling edge 0 7 -630 -630 1 0 70 70 2 0 150 150 3 0 230 230 4 0 330 330 5 0 430 430 6 0 530 530 7 0 620 620 congfig3 setting datadly clkdly 0 0 310 310 0 1 390 390 0 2 480 480 0 3 560 560 0 4 650 650 0 5 740 740 hold d[x..0] valid to dataclk rising or t h(data) 0 6 850 850 ps time falling edge 0 7 930 930 1 0 200 200 2 0 100 100 3 0 20 20 4 0 -60 -60 5 0 -140 -140 6 0 -220 -220 7 0 -290 -290 copyright ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com typical characteristics all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 3. dac3154 integral nonlinearity figure 4. dac3154 differential nonlinearity figure 5. dac3154 sfdr vs output frequency over input figure 6. dac3154 second-order harmonic distortion vs scale output frequency over input scale figure 7. dac3154 third-order harmonic distortion vs figure 8. dac3154 sfdr vs output frequency over f dac output frequency over input scale 14 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0 200 400 600 800 1000 code dnl (lsb) g004 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (mhz) sfdr (dbc) f dac = 200 msps f dac = 300 msps f dac = 400 msps f dac = 500 msps g008 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) hd3 (dbc) 0dbfs?6dbfs ?12dbfs g007 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) sfdr (dbc) 0dbfs?6dbfs ?12dbfs g005 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) hd2 (dbc) 0dbfs?6dbfs ?12dbfs g006 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0 200 400 600 800 1000 code inl (lsb) g003
dac3154 dac3164 www.ti.com slas960 ? may 2013 typical characteristics (continued) all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 9. dac3154 imd3 vs output frequency over input figure 10. dac3154 imd3 vs output frequency over f dac scale figure 11. dac3154 nsd vs output frequency over input figure 12. dac3154 nsd vs output frequency over f dac scale figure 13. dac3154 aclr (adjacent channel) vs output figure 14. dac3154 aclr (alternate channel) vs output frequency frequency copyright ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: dac3154 dac3164 ?100 ?90 ?80 ?70 ?60 ?50 0 50 100 150 200 250 output frequency (mhz) aclr (dbc) adjacent channel f dac = 500 msps g013 ?100 ?90 ?80 ?70 ?60 ?50 0 50 100 150 200 250 output frequency (mhz) aclr (dbc) alternate channel f dac = 500 msps g012 100 110 120 130 140 150 160 170 0 50 100 150 200 250 output frequency (db) nsd (dbc/hz) 0dbfs?6dbfs ?12dbfs g011 100 110 120 130 140 150 160 170 0 100 200 250 output frequency (mhz) nsd (dbc/hz) f dac = 200 msps f dac = 300 msps f dac = 400 msps f dac = 500 msps g012 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) imd3 (dbc) 0dbfs?6dbfs ?12dbfs g009 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (mhz) imd3 (dbc) f dac = 200 msps f dac = 300 msps f dac = 400 msps f dac = 500 msps g010
dac3154 dac3164 slas960 ? may 2013 www.ti.com typical characteristics (continued) all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 15. dac3154 single-tone spectral plot (if = 20mhz) figure 16. dac3154 single-tone spectral plot (if = 70mhz) figure 17. dac3154 two-tone spectral plot (if = 20mhz) figure 18. dac3154 two-tone spectral plot (if = 70mhz) figure 19. dac3154 acpr four-carrier figure 20. dac3154 acpr single-carrier wcdma test mode 1 wcdma test mode 1 16 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 50 90 130 170 210 250 frequency (mhz) power (dbm) f dac = 491. 52msps f out = 20 mhz g011 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 50 90 130 170 210 250 frequency (mhz) power (dbm) f dac = 491. 52msps f out = 70 mhz g016 a * 3 d b r b w 3 0 k h z v b w 3 0 0 k h z * s w t 2 s * r e f - 2 0 d b m a t t 5 d b c l r w r * 1 r m n o r * c e n t e r 7 0 m h z s p a n 4 0 . 8 m h z 4 . 0 8 m h z / - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 s t a n d a r d : w - c d m a 3 g p p f w d t x c h a n n e l s c h 1 - 1 8 . 6 2 d b m ( r e f ) c h 2 - 1 8 . 6 4 d b m c h 3 - 1 8 . 7 2 d b m c h 4 - 1 8 . 7 0 d b m t o t a l - 1 2 . 6 5 d b m a d j a c e n t c h a n n e l l o w e r - 6 1 . 2 4 d b u p p e r - 6 1 . 3 4 d b a l t e r n a t e c h a n n e l l o w e r - 6 1 . 1 1 d b u p p e r - 6 1 . 3 9 d b a * r e f - 1 0 d b m * * 3 d b r b w 3 0 k h z v b w 3 0 0 k h z s w t 2 s a t t 5 d b c l r w r * 1 r m n o r * c e n t e r 7 0 m h z s p a n 1 5 . 5 m h z 1 . 5 5 m h z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 t x c h a n n e l w - c d m a 3 g p p f w d b a n d w i d t h 3 . 8 4 m h z p o w e r - 1 0 . 6 4 d b m a d j a c e n t c h a n n e l b a n d w i d t h 3 . 8 4 m h z l o w e r - 6 9 . 1 1 d b s p a c i n g 5 m h z u p p e r - 6 9 . 1 5 d b ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 15 17 19 21 23 25 frequency (mhz) power (dbm) f dac = 500 msps f out = 20 mhz tone spacing = 1 mhz g017 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 65 67 69 71 73 75 frequency (mhz) power (dbm) f dac = 500 msps f out = 70 mhz tone spacing = 1 mhz g018
dac3154 dac3164 www.ti.com slas960 ? may 2013 typical characteristics (continued) all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 21. dac3154 acpr lte 10-mhz fdd e-tm 1.1 figure 22. dac3154 acpr lte 20-mhz fdd e-tm 1.1 figure 23. dac3154 power consumption vs f dac figure 24. dac3164 integral nonlinearity figure 25. dac3164 differential nonlinearity copyright ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: dac3154 dac3164 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 code inl (lsb) g024 ?0.2 ?0.15 ?0.1 ?0.05 0 0.05 0.1 0.15 0.2 0 500 1000 1500 2000 2500 3000 3500 4000 code dnl (lsb) g025 100 200 300 400 500 600 200 300 400 500 f dac (msps) power (mw) qmc on g023 a r e f - 1 0 d b m * a t t 5 d b c l r w r * 1 r m * * n o r 3 d b r b w 3 0 k h z v b w 3 0 0 k h z s w t 2 s * c e n t e r 7 0 m h z s p a n 2 9 . 2 8 2 7 4 1 9 m h z 2 . 9 2 8 2 7 4 1 9 m h z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 t x c h a n n e l e - u t r a / l t e s q u a r e b a n d w i d t h 9 . 0 1 5 m h z p o w e r - 1 2 . 3 3 d b m a d j a c e n t c h a n n e l b a n d w i d t h 9 . 0 1 5 m h z l o w e r - 6 4 . 0 0 d b s p a c i n g 1 0 m h z u p p e r - 6 4 . 0 9 d b a r e f - 1 0 d b m * * * 3 d b r b w 3 0 k h z v b w 3 0 0 k h z s w t 2 s a t t 5 d b c l r w r * 1 r m n o r * c e n t e r 7 0 m h z s p a n 5 8 . 5 5 0 3 4 5 3 8 m h z 5 . 8 5 5 0 3 4 5 3 8 m h z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 t x c h a n n e l e - u t r a / l t e s q u a r e b a n d w i d t h 1 8 . 0 1 5 m h z p o w e r - 1 1 . 1 4 d b m a d j a c e n t c h a n n e l b a n d w i d t h 1 8 . 0 1 5 m h z l o w e r - 6 1 . 9 3 d b s p a c i n g 2 0 m h z u p p e r - 6 2 . 2 1 d b
dac3154 dac3164 slas960 ? may 2013 www.ti.com typical characteristics (continued) all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 26. dac3164 sfdr vs output frequency over input figure 27. dac3164 second-order harmonic distortion vs scale output frequency over input scale figure 28. dac3164 third-order harmonic distortion vs figure 29. dac3164 sfdr vs output frequency over f dac output frequency over input scale figure 30. dac3164 imd3 vs output frequency over input figure 31. dac3164 imd3 vs output frequency over f dac scale 18 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) sfdr (dbc) 0dbfs?6dbfs ?12dbfs g026 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) hd2 (dbc) 0dbfs?6dbfs ?12dbfs g027 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) imd3 (dbc) 0dbfs?6dbfs ?12dbfs g030 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (mhz) imd3 (dbc) f dac = 200 msps f dac = 300 msps f dac = 400 msps f dac = 500 msps g031 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (db) hd3 (dbc) 0dbfs?6dbfs ?12dbfs g028 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 output frequency (mhz) sfdr (dbc) f dac = 200 msps f dac = 300 msps f dac = 400 msps f dac = 500 msps g029
dac3154 dac3164 www.ti.com slas960 ? may 2013 typical characteristics (continued) all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 32. dac3164 nsd vs output frequency over input figure 33. dac3164 nsd vs output frequency over f dac scale figure 34. dac3164 aclr (adjacent channel) vs output figure 35. dac3164 aclr (alternate channel) vs output frequency frequency figure 36. dac3164 single-tone spectral plot (if = 20mhz) figure 37. dac3164 single-tone spectral plot (if = 70mhz) copyright ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: dac3154 dac3164 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 50 90 130 170 210 250 frequency (mhz) power (dbm) f dac = 491. 52msps f out = 20 mhz g036 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 50 90 130 170 210 250 frequency (mhz) power (dbm) f dac = 491. 52msps f out = 70 mhz g037 ?100 ?90 ?80 ?70 ?60 ?50 0 50 100 150 200 250 output frequency (mhz) aclr (dbc) adjacent channel f dac = 500 msps g034 ?100 ?90 ?80 ?70 ?60 ?50 0 50 100 150 200 250 output frequency (mhz) aclr (dbc) alternate channel f dac = 500 msps g035 110 120 130 140 150 160 170 180 0 50 100 150 200 250 output frequency (db) nsd (dbc/hz) 0dbfs?6dbfs ?12dbfs g032 110 120 130 140 150 160 170 180 0 100 200 250 output frequency (mhz) nsd (dbc/hz) f dac = 200 msps f dac = 300 msps f dac = 400 msps f dac = 500 msps g033
dac3154 dac3164 slas960 ? may 2013 www.ti.com typical characteristics (continued) all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 38. dac3164 two-tone spectral plot (if = 20mhz) figure 39. dac3164 two-tone spectral plot (if = 70mhz) figure 40. dac3164 acpr four-carrier figure 41. dac3164 acpr single-carrier wcdma test mode 1 wcdma test mode 1 figure 42. dac3164 acpr lte 10-mhz fdd e-tm 1.1 figure 43. dac3164 acpr lte 20-mhz fdd e-tm 1.1 20 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 a * * * 3 d b r b w 3 0 k h z v b w 3 0 0 k h z s w t 2 s r e f - 1 0 d b m a t t 5 d b c l r w r * 1 r m n o r * c e n t e r 7 0 m h z s p a n 1 5 . 5 m h z 1 . 5 5 m h z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 t x c h a n n e l w - c d m a 3 g p p f w d b a n d w i d t h 3 . 8 4 m h z p o w e r - 1 0 . 7 0 d b m a d j a c e n t c h a n n e l b a n d w i d t h 3 . 8 4 m h z l o w e r - 7 7 . 8 4 d b s p a c i n g 5 m h z u p p e r - 7 7 . 1 4 d b ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 15 17 19 21 23 25 frequency (mhz) power (dbm) f dac = 500 msps f out = 20 mhz tone spacing = 1 mhz g038 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 65 67 69 71 73 75 frequency (mhz) power (dbm) f dac = 500 msps f out = 70 mhz tone spacing = 1 mhz g039 a * r e f - 2 0 d b m * * 3 d b r b w 3 0 k h z v b w 3 0 0 k h z s w t 2 s a t t 5 d b c l r w r * 1 r m n o r * c e n t e r 7 0 m h z s p a n 2 9 . 2 8 2 7 4 1 9 m h z 2 . 9 2 8 2 7 4 1 9 m h z / - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 t x c h a n n e l e - u t r a / l t e s q u a r e b a n d w i d t h 9 . 0 1 5 m h z p o w e r - 1 2 . 3 7 d b m a d j a c e n t c h a n n e l b a n d w i d t h 9 . 0 1 5 m h z l o w e r - 7 3 . 6 7 d b s p a c i n g 1 0 m h z u p p e r - 7 3 . 4 6 d b a * * * 3 d b r b w 3 0 k h z v b w 3 0 0 k h z s w t 2 s r e f - 2 0 d b m a t t 5 d b c l r w r * 1 r m n o r * c e n t e r 7 0 m h z s p a n 5 8 . 5 5 0 3 4 5 3 8 m h z 5 . 8 5 5 0 3 4 5 3 8 m h z / - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 t x c h a n n e l e - u t r a / l t e s q u a r e b a n d w i d t h 1 8 . 0 1 5 m h z p o w e r - 1 1 . 2 0 d b m a d j a c e n t c h a n n e l b a n d w i d t h 1 8 . 0 1 5 m h z l o w e r - 7 0 . 9 1 d b s p a c i n g 2 0 m h z u p p e r - 7 0 . 6 6 d b a r e f - 1 0 d b m * * 3 d b r b w 3 0 k h z v b w 3 0 0 k h z * s w t 2 s a t t 5 d b c l r w r * 1 r m n o r * c e n t e r 7 0 m h z s p a n 4 0 . 8 m h z 4 . 0 8 m h z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 s t a n d a r d : w - c d m a 3 g p p f w d t x c h a n n e l s c h 1 - 1 8 . 7 0 d b m ( r e f ) c h 2 - 1 8 . 6 9 d b m c h 3 - 1 8 . 7 7 d b m c h 4 - 1 8 . 7 5 d b m t o t a l - 1 2 . 7 1 d b m a d j a c e n t c h a n n e l l o w e r - 7 0 . 7 4 d b u p p e r - 7 0 . 8 7 d b a l t e r n a t e c h a n n e l l o w e r - 7 0 . 8 6 d b u p p e r - 7 0 . 8 4 d b
dac3154 dac3164 www.ti.com slas960 ? may 2013 typical characteristics (continued) all plots are at 25 c, nominal supply voltages, f dac = 500msps, 50% clock duty cycle, 0-dbfs input signal and 20ma full- scale output current (unless otherwise noted). figure 44. dac3164 power consumption vs f dac copyright ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: dac3154 dac3164 100 200 300 400 500 600 200 300 400 500 f dac (msps) power (mw) qmc on g044
dac3154 dac3164 slas960 ? may 2013 www.ti.com definition of specifications adjacent carrier leakage ratio (aclr): defined as the ratio in decible relative to the carrier (dbc) between the measured power within the channel and that of its adjacent channel. analog and digital power supply rejection ratio (apssr, dpssr): defined as the percentage error in the ratio of the delta iout and delta supply voltage normalized with respect to the ideal iout current. differential nonlinearity (dnl): defined as the variation in analog output associated with an ideal 1 lsb change in the digital input code. gain drift: defined as the maximum change in gain, in terms of ppm of full-scale range (fsr) per c, from the value at ambient (25 c) to values over the full operating temperature range. gain error: defined as the percentage error (in fsr%) for the ratio between the measured full-scale output current and the ideal full-scale output current. integral nonlinearity (inl): defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. intermodulation distortion (imd3): the two-tone imd3 is defined as the ratio (in dbc) of the 3rd-order intermodulation distortion product to either fundamental output tone. offset drift: defined as the maximum change in dc offset, in terms of ppm of full-scale range (fsr) per c, from the value at ambient (25 c) to values over the full operating temperature range. offset error: defined as the percentage error (in fsr%) for the ratio between the measured mid-scale output current and the ideal mid-scale output current. output compliance range: defined as the minimum and maximum allowable voltage at the output of the current-output dac. exceeding this limit may result reduced reliability of the device or adversely affecting distortion performance. reference voltage drift: defined as the maximum change of the reference voltage in ppm per degree celsius from value at ambient (25 c) to values over the full operating temperature range. spurious free dynamic range (sfdr): defined as the difference (in dbc) between the peak amplitude of the output signal and the peak spurious signal. signal to noise ratio (snr): defined as the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral components below the nyquist frequency, including noise, but excluding the first six harmonics and dc. timing diagrams figure 45. dac3154 input timing diagram for dual channel ddr mode 22 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 a 4 [9:0] b 4 [9:0] d[9:0]p/n dataclkp/n (ddr) syncp/n resets write pointer to position 0 t s(data) t h(data) t s(data) t h(data) t s(data) t h(data) a 3 [9:0] b 3 [9:0] a 6 [9:0] b 6 [9:0] a 5 [9:0] b 5 [9:0] a 7 [9:0] b 7 [9:0]
dac3154 dac3164 www.ti.com slas960 ? may 2013 figure 46. dac3154 input timing diagram for single channel sdr mode figure 47. dac3164 input timing diagram for dual channel ddr mode figure 48. dac3164 input timing diagram for single channel sdr mode copyright ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: dac3154 dac3164 a 5 [11:0] a 6 [11:0] d[11:0]p/n dataclkp/n (sdr) syncp/n resets write pointer to position 0 t s(data) t h(data) t s(data) t h(data) a 3 [11:0] a 4 [11:0] a 9 [11:0] a 10 [11:0] a 7 [11:0] a 11 [11:0] a 8 [11:0] a 4 [11:0] b 4 [11:0] d[11:0]p/n dataclkp/n (ddr) syncp/n resets write pointer to position 0 t s(data) t h(data) t s(data) t h(data) t s(data) t h(data) a 3 [11:0] b 3 [11:0] a 6 [11:0] b 6 [11:0] a 5 [11:0] b 5 [11:0] a 7 [11:0] b 7 [11:0] a 5 [9:0] a 6 [9:0] d[9:0]p/n dataclkp/n (sdr) syncp/n resets write pointer to position 0 t s(data) t h(data) t s(data) t h(data) a 3 [9:0] a 4 [9:0] a 9 [9:0] a 10 [9:0] a 7 [9:0] a 11 [9:0] a 8 [9:0]
dac3154 dac3164 slas960 ? may 2013 www.ti.com data input formats table 1. dac3154 dual channel ddr mode bits differential pair (p/n) dataclk rising edge dataclk falling edge d9 a9 b9 d8 a8 b8 d7 a7 b7 d6 a6 b6 d5 a5 b5 d4 a4 b4 d3 a3 b3 d2 a2 b2 d1 a1 b1 d0 a0 b0 sync fifo write reset ? table 2. dac3154 single channel sdr mode bits differential pair (p/n) dataclk rising edge dataclk falling edge d9 a9 d8 a8 d7 a7 d6 a6 d5 a5 d4 a4 d3 a3 d2 a2 d1 a1 d0 a0 sync fifo write reset ? table 3. dac3164 dual channel ddr mode bits differential pair (p/n) dataclk rising edge dataclk falling edge d11 a11 b11 d10 a10 b10 d9 a9 b9 d8 a8 b8 d7 a7 b7 d6 a6 b6 d5 a5 b5 d4 a4 b4 d3 a3 b3 d2 a2 b2 d1 a1 b1 d0 a0 b0 sync fifo write reset ? 24 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 table 4. dac3164 single channel ddr mode bits differential pair (p/n) dataclk rising edge dataclk falling edge d11 a11 d10 a10 d9 a9 d8 a8 d7 a7 d6 a6 d5 a5 d4 a4 d3 a3 d2 a2 d1 a1 d0 a0 sync fifo write reset ? copyright ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com serial interface description the serial port of the dac3154/dac3164 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. the interface provides read/write access to all registers used to define the operating modes of dac3154/dac3164. it is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by sif4_ena in register config0, bit9. in both configurations, sclk is the serial interface input clock and sdenb is serial interface enable. for 3 pin configuration, sdio is a bidirectional pin for both data in and data out. for 4 pin configuration, sdio is data in only and sdo is data out only. data is input into the device with the rising edge of sclk. data is output from the device on the falling edge of sclk. each read/write operation is framed by signal sdenb (serial data enable bar) asserted low. the first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. table 5 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. the data transfer cycle consists of two bytes. table 5. instruction byte of the serial interface msb lsb bit 7 6 5 4 3 2 1 0 description r/w a6 a5 a4 a3 a2 a1 a0 r/w identifies the following data transfer cycle as a read or write operation. a high indicates a read operation from dac3154/dac3164 and a low indicates a write operation to dac3154/dac3164. [a6 : a0] identifies the address of the register to be accessed during the read or write operation. figure 49 shows the serial interface timing diagram for a dac3154/dac3164 write operation. sclk is the serial interface clock input to dac3154/dac3164. serial data enable sdenb is an active low input to dac3154/dac3164. sdio is serial data in. input data to dac3154/dac3164 is clocked on the rising edges of sclk. figure 49. serial interface write timing diagram figure 50 shows the serial interface timing diagram for a dac3154/dac3164 read operation. sclk is the serial interface clock input to dac3154/dac3164. serial data enable sdenb is an active low input to dac3154/dac3164. sdio is serial data in during the instruction cycle. in 3 pin configuration, sdio is data out from the dac3154/dac3164 during the data transfer cycle, while sdo is in a high-impedance state. in 4 pin configuration, both sdio and sdo are data out from the dac3154/dac3164 during the data transfer cycle. at the end of the data transfer, sdio and sdo will output low on the final falling edge of sclk until the rising edge of sdenb when they will 3-state. 26 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 rwb a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 instruction cycle data transfer cycle t s (sdenb) t s (sdio) t h (sdio) t sclk sdenb sclk sdio sdenb sclk sdio
dac3154 dac3164 www.ti.com slas960 ? may 2013 figure 50. serial interface read timing diagram register descriptions in the sif interface there are four types of registers: normal: the normal register type allows data to be written and read from. all 16-bits of the data are registered at the same time. there is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. there are three subtypes of normal: autosync: a normal register that causes a sync to be generated after the write is finished. these are most commonly used in things like offsets and phaseadd where there is a word or block setup that extends across multiple registers and all of the registers need to be programmed before any take effect on the circuit. for example, the phaseadd is two registers long. it wouldn ? t serve the user to have the first write 16 of the 32 bits cause a change in the frequency, so the design allows all the registers to be written and then when that last one for this block is finished, an autosync is generated for the mixer telling it to grab all the new sif values. this will occur on a mixer clock cycle so that no meta-stability errors occur. no reset value: these are normal registers, but for one reason or another reset value can not be guaranteed. this could be because the register has some read_only bits or some internal logic partially controls the bit values. an example is the sif_config6 register. the bits come from the temperature sensor and the fuses. depending on which fuses are blown and what the die temp is the reset value will be different. fuse controlled: while this isn ? t a type of register, you may see this description in the area describing the default value for the register. what is means is that fuses will change the default value and the value shown in the document is for when no fuses are blown. read_only: registers that are internal wires anded with the address bus then connected to the sif output data bus. write_to_clear: these registers are just like normal registers with one exception. they can be written and read, however, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is written to ? 0 ? . this way interrupts will be captured and stay constant until cleared by the user. copyright ? 2013, texas instruments incorporated submit documentation feedback 27 product folder links: dac3154 dac3164 rwb a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 instruction cycle data transfer cycle t d (data) sdenb sclk sdio sdenb sclk sdio sdo d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo data n data n-1
dac3154 dac3164 slas960 ? may 2013 www.ti.com table 6. register map (msb) (lsb) name address default bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 15 bit 0 config0 0x00 0x44fc qmc_ dual_ ena chipwidth (1:0) reserved twos sif4_ena reserve fifo_ ena alarm_ alarm_ alignrx_en syncrx_en lvdsdataclk_ reserved synconly_en offset_ena d out_ena out_pol a a ena a config1 0x01 0x600e iotest_ena bsideclk_e fullword_i 64cnt_ena dacclkgon dataclkgone collision_ena reserve daca_ dacb_ sif_sync sif_ alarm_ alarm_1awa alarm_coll reserved na nterface_ e_ ena _ena d compliment complime sync_ena 2away_en y_ena ision _ena ena nt a config2 0x02 0x3fff reserved lvdsdata_ena (13:0) config3 0x03 0x0000 datadlya (2:0) clkdlya (2:0) datadlyb (2:0) clkdlyb (2:0) extref_ena reserved dual_ena config4 0x04 0x0000 reserved iotest_results (13:0) config5 0x05 0x0000 alarm_fro alarm_fro alarms_from_fifoa (2:0) alarms_from_fifob (2:0) alarm_dacclk alarm_dat clock_gon alarm_fro alarm_fro reserved m_ m_ _ gone aclk_ e m_ iotesta m_ iotestb zerochka zerochkb gone config6 0x06 0x0084(d tempdata (7:0) fuse_cntl (5:0) reserved ac3164) 0x0088(d ac3154) config7 0x07 0xffff alarms_mask (15:0) config8 0x08 0x4000 reserved qmc_offseta (12:0) config9 0x09 0x8000 fifo_offset (2:0) qmc_offsetb (12:0) config10 0x0a 0xf080 coarse_dac (3:0) fuse_ reserved reserved tsense_ clkrecv_ena sleepa sleepb reserved sleep sleep config11 0x0b 0x1111 reserved reserved reserved reserved config12 0x0c 0x3a7a reserved iotest_pattern0 (13:0) config13 0x0d 0x36b6 reserved iotest_pattern1 (13:0) config14 0x0e 0x2aea reserved iotest_pattern2 (13:0) config15 0x0f 0x0545 reserved iotest_pattern3 (13:0) config16 0x10 0x1a1a reserved iotest_pattern4 (13:0) config17 0x11 0x1616 reserved iotest_pattern5 (13:0) config18 0x12 0x2aaa reserved iotest_pattern6 (13:0) config19 0x13 0x06c6 reserved iotest_pattern7 (13:0) config20 0x14 0x0000 sifdac_ reserved sifdac (13:0) ena config21 0x15 0xffff sleepcntl (15:0) config22 0x16 0x0000 fa002_data(15:0) config23 0x17 0x0000 fa002_data(31:16) config24 0x18 0x0000 fa002_data(47:32) config25 0x19 0x0000 fa002_data(63:48) config127 0x7f 0x0044 reserved reserved reserved reserved reserved titest_voh titest_vol vendorid (1:0) versionid (2:0) 28 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 register name: config0 ? address: 0x00, default: 0x44fc register addr bit name function default value name (hex) config0 0x00 15 qmc_offset_ena enable the offset function when asserted. 0 14 dual_ena utilizes both dacs when asserted. 1 fuse controlled 13:12 chipwidth programmable bits for setting the input interface width. 00 00: all 14 bits are used. note: not applicable to dac3154/dac3164. 01: upper 12 bits are used 10: upper 10 bits are used 11: upper 10 bits are used 11 reserved reserved 0 10 twos when asserted, this bit tells the chip to presume 2 ? s 1 complement data is arriving at the input. otherwise offset binary is presumed. 9 sif4_ena when asserted the sif interface becomes a 4 pin interface. 0 this bit has a lower priority than the dieid_ena bit. 8 reserved reserved 0 7 fifo_ena when asserted, the fifo is absorbing the difference between 1 input clock and dac clock. if it is not asserted then the fifo buffering is bypassed but the reversing of bits and handling of offset binary input is still available. note: when the fifo is bypassed the daccclk and dataclk must be aligned or there may be timing errors; and, it is not recommended for actual application use. 6 alarm_out_ena when asserted the pin alarm becomes an output instead of a 1 tri-stated pin. 5 alarm_out_pol this bit changes the polarity of the alarm signal. 1 (0=negative logic, 1=positive logic) 4 alignrx_ena when asserted the align pin receiver is powered up. note: 1 it is recommended to clear this bit when alignp/n are not used. 3 syncrx_ena when asserted the sync pin receiver is powered up. note: 1 it is recommended to clear this bit when syncp/n are not used. 2 lvdsdataclk_ena when asserted the dataclk pin receiver is powered up. 1 1 reserved reserved 0 0 synconly_ena when asserted the chip is put into the sync only mode 0 where the sync pin is used as the sync input for both the front and back of the fifo. copyright ? 2013, texas instruments incorporated submit documentation feedback 29 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com register name: config1 ? address: 0x01, default: 0x600e register addr default bit name function name (hex) value config1 0x01 15 iotest_ena turns on the io-testing circuitry when asserted. this is the circuitry 0 that will compare a 8 sample input pattern to sif programmed registers to make sure the data coming into the chip meets setup/hold requirements. if this bit is a ? 0 ? then the clock to this circuitry is turned off for power savings. note: sample 0 should be aligned with the rising edge of sync. 14 bsideclk_ena when asserted the input clock for the b side datapath is enabled. 1 otherwise the io test and the fifo on the b side of the design will not get a clock. 13 reserved reserved. 1 12 64cnt_ena this enables the resetting of the alarms after 64 good samples with 0 the goal of removing unnecessary errors. for instance on a lab board, when checking the setup/hold through io test, there may initially be errors, but once the test is up and running everything works. setting this bit removes the need for a sif write to clear the alarm register. 11 dacclkgone_ena this allows the dacclk gone signal from the clock monitor to be 0 used to shut the output off. 10 dataclkgone_end this allows the dataclk gone signal from the clock monitor to be 0 used to shut the output off. 9 collision_ena this allows the collision alarm from the fifo to shut the output off 0 8 reserved reserved. 0 7 daca_compliment when asserted the output to the daca is complimented. this 0 allows the user of the chip to effectively change the + and ? designations of the dac output pins. 6 dacb_compliment when asserted the output to the dacb is complimented. this 0 allows the user of the chip to effectively change the + and ? designations of the dac output pins. 5 sif_sync this is the sif_sync signal. whatever is programmed into this bit 0 will be used as the chip sync when sif_sync mode is enabled. design is sensitive to rising edges so programming from 0- > 1 is when the sync pulse is generated. 1- > 0 has no effect. 4 sif_sync_ena when asserted enable sif_sync mode. 0 3 alarm_2away_ena when asserted alarms from the fifo that represent the pointers 1 being 2 away are enabled 2 alarm_1away_ena when asserted alarms from the fifo that represent the pointers 1 being 1 away are enabled 1 alarm_collision_ena when asserted the collision of fifo pointers causes an alarm to be 1 generated 0 reserved reserved 0 register name: config2 ? address: 0x02, default: 0x3fff register addr bit name function default value name (hex) config2 0x02 15 reserved reserved 0 14 reserved reserved 0 13:0 lvdsdata_ena these 14 bits are individual enables for the 14 input pin receivers. 0x3fff note: it is recommended to clear bit (1:0) for the 12-bit dac3164, and clear bit (3:0) for the 10-bit dac3154. 30 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 register name: config3 ? address: 0x03, default: 0x0000 register addr bit name function default value name (hex) config3 0x03 15:13 datadlya controls the delay of the a data inputs through the lvds receivers. 000 0= no additional delay and each lsb adds a nominal 80ps. 12:10 clkdlya controls the delay of the a data clock input through the lvds 000 receivers. 0= no additional delay and each lsb adds a nominal 80ps. 9:7 datadlyb controls the delay of the b data inputs through the lvds receivers. 000 0= no additional delay and each lsb adds a nominal 80ps. 6:4 clkdlyb controls the delay of the b data clock input through the lvds 000 receivers. 0= no additional delay and each lsb adds a nominal 80ps. 3 extref_ena enable external reference for the dac when set. 0 2:1 reserved reserved 00 0 dual_clock_ena when asserted it tells the lvds input circuit that there are two 0 individual data clocks. note: must be in sif_sync mode, and not applicable to dac3154/dac3164. register name: config4 ? address: 0x04, default: 0x0000 register addr default bit name function name (hex) value config4 0x04 15:14 reserved reserved 00 write to 13:0 iotest_ results the values of these bits tell which bit in the input word failed during the 0x0000 clear/ io-test pattern comparison. bit 13 corresponds to the msb input. no reset value copyright ? 2013, texas instruments incorporated submit documentation feedback 31 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com register name: config5 ? address: 0x05, default: 0x0000 register addr default bit name function name (hex) value config5 0x05 15 alarm_from_ zerochka when this bit is asserted the fifo a write pointer has an all zeros 0 write to pattern in it. since this pointer is a shift register, all zeros will cause clear the input point to be stuck until the next sync. the result could be a repeated 8t pattern at the output if the mixer is off and no syncs occur. check for this error will tell the user that another sync is necessary to restart the fifo write pointer. 14 alarm_from_ zerochkb when this bit is asserted the fifo b write pointer has an all zeros 0 pattern in it. since this pointer is a shift register, all zeros will cause the input point to be stuck until the next sync. the result could be a repeated 8t pattern at the output if the mixer is off and no syncs occur. check for this error will tell the user that another sync is necessary to restart the fifo write pointer. 13:11 alarms_from_ fifoa these bits report the fifo a pointer status. 000 000: all fine 001: pointers are 2 away 01x: pointers are 1 away 1xx: fifo pointer collision 10:8 alarms_from_ fifob these bits report the fifo b pointer status. 0 000: all fine 001: pointers are 2 away 01x: pointers are 1 away 1xx: fifo pointer collision 7 alarm_dacclk_ gone bit gets asserted when the dacclk has been stopped long for 0 enough cycles to be caught. the number of cycles varies with interpolation. 6 alarm_dataclk_ gone bit gets asserted when the dataclk has been stopped long for 0 enough cycles to be caught. the number of cycles varies with interpolation. 5 clock_gone this bit gets set when either alarm_dacclk_gone or 0 alarm_dataclk_gone are asserted. it controls the output of the cdrv_ser block. when high, the cdrv_ser block will output ? 0x8000 ? for each output connected to a dac. the bit must be written to ? 0 ? for cdrv_ser outputs to resume normal operation. 4 alarm_from_ iotesta this is asserted when the input data pattern does not match the 0 pattern in the iotest_pattern registers. 3 alarm_from_ iotestb this is asserted when the input data pattern does not match the 0 pattern in the iotest_pattern registers. 2 reserved reserved 0 1 reserved reserved 0 0 reserved reserved 0 32 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 register name: config6 ? address: 0x06, default: 0x0084 (dac3164); 0x0088 (dac3154) register addr default bit name function name (hex) value config6 0x06 15:8 tempdata this the output from the chip temperature sensor. 0x00 no reset note: when reading these bits the sif interface must be exteremly value slow, 1mhz range. 7:2 fuse_cntl these are the values of the blown fuses and are used to determine the 0x21 for available functionality in the chip. dac3164; 0x22 for note: these bits are read_only and allow the user to check dac3154 what features have been disabled in the device. bit5 = 1: force full word interface. bit4 = 1: reserved bit3 = 1: reserved bit2 = 1: forces single dac mode. note: this does not force the channel b in sleep mode. in order to do so, user needs to program the sleepb spi bit (config10, bit 5) to "1". bit1:0 : forces a different bits size. ? 00 ? 14bit. ? 01 ? 12bit ? 10 ? 10bit ? 11 ? 10bit 1 reserved reserved 0 0 reserved reserved 0 register name: config7 ? address: 0x07, default: 0xffff register addr default bit name function name (hex) value config7 0x07 15:0 alarms_ mask each bit is used to mask an alarm. assertion masks the alarm: bit15 = 0xffff alarm_mask_zerochka bit14 = alarm_mask_zerochkb bit13 = alarm_mask_fifoa_collision bit12 = alarm_mask_fifoa_1away bit11 = alarm_mask_fifoa_2away bit10 = alarm_mask_fifob_collision bit9 = alarm_mask_fifob_1away bit8 = alarm_mask_fifob_2away bit7 = alarm_mask_dacclk_gone bit6 = alarm_mask_dataclk_gone bit5 = masks the signal which turns off the dac output when a clock or collision occurs. this bit has no effect on the pad_alarm output. bit4 = alarm_mask_iotesta bit3 = alarm_mask_iotestb bit2 = bit1 = bit0 = register name: config8 ? address: 0x08, default: 0x4000 register addr default bit name function name (hex) value config8 0x08 15:13 reserved reserved 010 12:0 qmc_ offseta the dac a offset correction. the offset is measured in dac lsbs. 0x0000 copyright ? 2013, texas instruments incorporated submit documentation feedback 33 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com register name: config9 ? address: 0x09, default: 0x8000 register addr default bit name function name (hex) value config9 0x09 15:13 fifo_ offset this is the starting point for the read_pointer in the fifo block. 100 the read_pointer is set to this location when a sync occurs on the auto dacclk side of the fifo. sync 12:0 qmc_ offsetb the dac b offset correction. the offset is measured in dac lsbs. 0x0000 note: writing this register causes an autosync to be generated in the qmoffset block. register name: config10 ? address: 0x0a, default: 0xf080 register addr default bit name function name (hex) value config10 0x0a 15:12 coarse_ dac scales the output current is 16 equal steps. 1111 11 fuse_ sleep put the fuses to sleep when set high. 0 10 reserved reserved 0 9 reserved reserved 0 8 tsense_ sleep when asserted the temperature sensor is put to sleep. 0 7 clkrecv_ena turn on the dac clock receiver block when asserted. 1 6 sleepa when asserted daca is put to sleep. 0 5 sleepb when asserted dacb is put to sleep. note: this bit needs to be 0 programmed to "1" for single dac mode. 4:0 reserved reserved 00000 register name: config11 ? address: 0x0b, default: 0x1111 register addr bit name function default value name (hex) config11 0x0b 15:12 reserved reserved 0001 11:8 reserved reserved 0001 7:4 reserved reserved 0001 3:0 reserved reserved 0001 register name: config12 ? address: 0x0c, default: 0x3a7a register addr bit name function default value name (hex) config12 0x0c 15:14 reserved reserved 00 13:0 iotest_ pattern0 this is dataword0 in the io test pattern. it is used with the seven 0x3a7a other words to test the input data. note: this word should be aligned with the rising edge of sync when testing the io interface. register name: config13 ? address: 0x0d, default: 0x36b6 register addr bit name function default value name (hex) config13 0x0d 15:14 reserved reserved 00 13:0 iotest_ pattern1 this is dataword1 in the io test pattern. it is used with the seven 0x36b6 other words to test the input data. 34 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164 ( ) vrefio mem_coarse_daca + 1 rbias
dac3154 dac3164 www.ti.com slas960 ? may 2013 register name: config14 ? address: 0x0e, default: 0x2aea register addr bit name function default value name (hex) config14 0x0e 15:14 reserved reserved 00 13:0 iotest_ pattern2 this is dataword2 in the io test pattern. it is used with the seven 0x2aea other words to test the input data. register name: config15 ? address: 0x0f, default: 0x0545 register addr bit name function default value name (hex) config15 0x0f 15:14 reserved reserved 00 13:0 iotest_ pattern3 this is dataword3 in the io test pattern. it is used with the seven 0x0545 other words to test the input data. register name: config16 ? address: 0x10, default: 0x1a1a register addr bit name function default value name (hex) config16 0x10 15:14 reserved reserved 00 13:0 iotest_ pattern4 this is dataword4 in the io test pattern. it is used with the seven 0x1a1a other words to test the input data. register name: config17 ? address: 0x11, default: 0x1616 register addr bit name function default value name (hex) config17 0x11 15:14 reserved reserved 00 13:0 iotest_ pattern5 this is dataword5 in the io test pattern. it is used with the seven 0x1616 other words to test the input data. register name: config18 ? address: 0x12, default: 0x2aaa register addr bit name function default value name (hex) config18 0x12 15:14 reserved reserved 00 13:0 iotest_ pattern5 this is datawor6 in the io test pattern. it is used with the seven 0x2aaa other words to test the input data. register name: config19 ? address: 0x13, default: 0x06c6 register addr bit name function default value name (hex) config19 0x13 15:14 reserved reserved 00 13:0 iotest_ pattern7 this is dataword7 in the io test pattern. it is used with the seven 0x06c6 other words to test the input data. copyright ? 2013, texas instruments incorporated submit documentation feedback 35 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com register name: config20 ? address: 0x14, default: 0x0000 register addr bit name function default value name (hex) config20 0x14 15 sifdac_ ena when asserted the dac output is set to the value in sifdac. this 0 can be used for trim setting and other static tests. 14 reserved reserved 0 13:0 sifdac this is the value that is sent to the dacs when sifdac_ena is 0x0000 asserted. register name: config21 ? address: 0x15, default: 0xffff register addr bit name function default value name (hex) config21 0x15 15:0 sleepcntl this controls what blocks get sent a sleep signal when the 0xffff pad_sleep pin is asserted. programming a ? 1 ? in a bit will pass the sleep signal to the appropriate block. bit15 = dac a bit14 = dac b bit13 = fuse sleep bit12 = temperature sensor bit11 = clock receiver bit10 = lvds data receivers bit9 = lvds sync receiver bit8 = pecl align receiver bit7 = lvds dataclk receiver bit6 = bit5 = bit4 = bit3 = bit2 = bit1 = bit0 = register name: config22 ? address: 0x16 register addr bit name function default value name (hex) config22 0x16 15:0 fa002_ data(15:0) lower 16bits of the die id word read only register name: config23 ? address: 0x17 register addr bit name function default value name (hex) config23 0x17 15:0 fa002_ data(31:16) lower middle 16bits of the die id word read only register name: config24 ? address: 0x18, default register addr bit name function default value name (hex) config24 0x18 15:0 fa002_ data(47:32) upper middle 16bits of the die id word read only 36 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
dac3154 dac3164 www.ti.com slas960 ? may 2013 register name: config25 ? address: 0x19 register addr bit name function default value name (hex) config25 0x19 15:0 fa002_ data(63:48) upper 16bits of the die id word read only register name: config127 ? address: 0x7f, default: 0x0045 register addr default bit name function name (hex) value config127 0x7f 15:14 reserved reserved 00 read 13:12 reserved reserved 00 only/no 11:10 reserved reserved 00 reset value 9:8 reserved reserved 00 7 reserved reserved 0 6 titest_voh a fixed ? 1 ? that can be used to test the voh at the sif output. 1 5 titest_vol a fixed ? 0 ? that can be used to test the vol at the sif output. 0 4:3 vendorid fixed to "01". 01 2:0 versionid chip version. 001 synchronization modes there are three modes of syncing included in the dac3154/dac3164. ? normal dual sync ? the sync pin is used to align the input side of the fifo (write pointers) with the a(0) sample. the align pin is used to reset the output side of the fifo (read pointers) to the offset value. multiple chip alignment can be accomplished with this kind of syncing. ? sync only ? in this mode only the sync pin is used to sync both the read and write pointers of the fifo. there is an asynchornized handoff between the dataclk and dacclk when using this mode, therefore it is impossible to accurately align multiple chips closer than 2 or 3t. ? sif_sync ? when neither sync nor align are used, a programmable sync pulse can be used to sync the design. however, the same issues as sync only apply. there is an asynchornized handoff between the serial clock domain and the two sides of the fifo. because of the asynchronous nature of the sif_sync it is impossible to align the sync up with any sample at the input. note: when alignp/n are not used, it is recommended to clear the alignrx_ena register (config1, bit 4), and tie alignp to digvdd18 and alignn to ground. when syncp/n are not used, it is recommended to clear register syncrx_ena (config0, bit3), and the unused syncp/n pins can be left open or tied to ground. copyright ? 2013, texas instruments incorporated submit documentation feedback 37 product folder links: dac3154 dac3164
dac3154 dac3164 slas960 ? may 2013 www.ti.com alarm monitoring dac3154/dac3164 includes flexible alarm monitoring that can be used to alert a possible malfunction scenario. all alarm events can be accessed either through the sip registers and/or through the alarm pin. once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to allow further testing. the set of alarms includes the following conditions: zero check alarm ? alarm_from_zerochk. occurs when the fifo write pointer has an all zeros pattern. since the write pointer is a shift register, all zeros will cause the input point to be stuck until the next sync event. when this happens a sync to the fifo block is required. fifo alarms ? alarm_from_fifo. occurs when there is a collision in the fifo pointers or a collision event is close. ? alarm_fifo_2away. pointers are within two addresses of each other. ? alarm_fifo_1away. pointers are within one address of each other. ? alarm_fifo_collision. pointers are equal to each other. clock alarms ? clock_gone. occurs when either the dacclk or dataclock have been stopped. ? alarm_dacclk_gone. occurs when the dacclk has been stopped. ? alarm_dataclk_gone. occurs when the dataclk has been stopped. pattern checker alarm ? alarm_from_iotest. occurs when the input data pattern does not match the pattern key. to prevent unexpected dac outputs from propagating into the transmit channel chain, dac3154, dac3164 includes a feature that disables the outputs when a catastrophic alarm occurs. the catastrophic alarms include fifo pointer collision, the loss dacclk or the loss of dataclk. when any of these alarms occur the internal txenable signal is driven low, causing a zeroing of the data going to the dac in < 10t. one caveat is if both clocks stop, the circuit cannot determine clock loss so no alarms are generated; therefore, no zeroing of output data occurs. 38 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: dac3154 dac3164
package option addendum www.ti.com 11-jun-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) device marking (4/5) samples dac3154irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) call ti level-3-260c-168 hr -40 to 85 dac3154i dac3154irgct active vqfn rgc 64 250 green (rohs & no sb/br) call ti level-3-260c-168 hr -40 to 85 dac3154i DAC3164IRGCR active vqfn rgc 64 2000 green (rohs & no sb/br) call ti level-3-260c-168 hr -40 to 85 dac3164i dac3164irgct active vqfn rgc 64 250 green (rohs & no sb/br) call ti level-3-260c-168 hr -40 to 85 dac3164i (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 11-jun-2013 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant dac3154irgcr vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 dac3154irgct vqfn rgc 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 DAC3164IRGCR vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 dac3164irgct vqfn rgc 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 package materials information www.ti.com 11-jun-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) dac3154irgcr vqfn rgc 64 2000 336.6 336.6 28.6 dac3154irgct vqfn rgc 64 250 336.6 336.6 28.6 DAC3164IRGCR vqfn rgc 64 2000 336.6 336.6 28.6 dac3164irgct vqfn rgc 64 250 336.6 336.6 28.6 package materials information www.ti.com 11-jun-2013 pack materials-page 2

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